1. Field of the Invention
This application generally relates to semiconductor memories and more specifically to asynchronously controlling DRAM circuitry.
2. Description of the Related Art
Generally, DRAM is built as a separate integrated circuit chip from any digital logic, thus allowing for use of a specialized DRAM process and structures such as trench or other 3D capacitors. Such structures may be used to create high capacitance structures in small areas, thus leading to high DRAM cell density on the DRAM chips. However, these structures are not compatible with logic processes. Adding the high density DRAM cell to the logic process may lead to higher fabrication cost and greater yield problems due to the increase in process steps and complexity.
For memory on integrated circuit chips created through use of a logic process, SRAM memory has typically been used.; However, SRAM memory is often much less dense than DRAM memory. As a result, SRAM requires more space on a chip than DRAM does. Also, SRAM may require more power and generate a higher temperature than DRAM.
Furthermore, DRAM cells require refreshing at times, to avoid charge leakage and corresponding corruption of data. SRAM does not require refresh, due to a different cell structure. Similarly, the differing cell structure of DRAM and SRAM results in differing timing associated with read and write operations. However, it would be advantageous to make RAM available by using dense DRAM arrays without requiring logic designers to handle the complicated DRAM and refresh timing.
A method and apparatus for asynchronously controlling a dram array in an sram environment is described. In one embodiment, this is a method of arbitrating between a refresh request and an access request: Furthermore, the access request may be either a read or a write request. Moreover, the refresh request may be generated by a refresh control circuit within a circuit implementing the asynchronous control method.
In an alternate embodiment, this is an apparatus. The apparatus includes an arbitration circuit block which may receive a refresh request and an access request. Furthermore, the access request may come as a read request or a write request, which may be implemented as separate signals. Moreover, the apparatus may include a refresh circuit block which may generate refresh control signals and the refresh request signal for the arbitration circuit.